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02.04.24
Features * +5 or -5 V single power supply * 20 dB typical gain * 2.0 GHz typical -3 dB cutoff frequency * On-chip matching to 50 * 55 mA typical operating current * Differential input and output * Differential ECL compatible input
F0321818B
2 GHz Bandwidth
Limiting Amplifier
Applications * Post-amplifier of an optical receiver circuit up to 2.5 Gb/s * Logic gate buffer to interface between analog circuit and logic circuit
Functional Description The F0321818B is a stable GaAs integrated limiting amplifier for use in a post-amplifier of an optical receiver circuit up to 2.5 Gb/s. The F0321818B typically specifies a small signal gain of 20 dB (Rs=RL=50 ) with a 3 dB-cutoff-frequency of 2.0 GHz. It features single +5 or -5 V supply operation, excellent VSWR's of 1.1:1, and a typical dissipation current of 55 mA. The F0321818B can be also used as interface circuits in sensing systems and measurement instruments. Emitter coupled logic (ECL) or source coupled FET logic (SCFL) circuits are the most popular IC's for high speed digital circuits; the F0321818B operating under a differential ECL compatible input condition is the best choice as the interface IC to join analog circuits to ECL circuits or conventional GaAs logic IC's.
2 GHz Limiting Amplifier
Absolute Maximum Ratings
F0321818B
Ta=25 C, unless specified
Parameter Supply Voltage Supply Current Input Voltage Swing (AC) Output Voltage Ambient Operating Temperature Storage Temperature Symbol VDD IDD VIN+ , VOUTVOUT+ , VOUTTa Tstg Value VSS-0.5 to VSS+7 80 1 VDD-2.5 to VDD 0 to +70 -55 to +125 Units V mA V V C C
Recommended Operating Conditions VSS = GND
Value Parameter Supply Voltage AC Coupled Load Ambient Operating Temperature Symbol Min. VDD RL Ta 4.75 0 Typ. 5 50 25 Max. 5.46 70 V C Units
Electrical Characteristics Ta = 25 C, VDD = +5 V, VSS = GND, unless specified
Value Parameter Supply Current Input Bias Point Output bias Point VSWR (IN, OUT) Gain -3dB High Frequency Cutoff Maximum Output Swing (single output) Symbol IDD VIN VOUT SWR GV Fc Vom Pin=-40dBm f=1MHz Pin=-40dBm RL=50 f=1MHz Pin=-40dBm RL=50 RL=50 Test Conditions Min. Pin=-40dBm 18 0.4 Typ. 55 1.5 3.5 1.1 20 2.0 0.6 Max. 70 1.8 0.8 mA V V dB GHz V Units
2 GHz Limiting Amplifier
Block Diagram
VDD
F0321818B
LPF+
VIN+ Amp. VINAmp. Output Buffer
VOUT+ VOUT-
LPF-
VSS
Dia Descriptions
VIN+ LPF+ VINLPFVOUT+ VOUTVSS1 VSS2 VDD VDD
Input AC Ground Input AC Ground Output Output Supply Voltage Supply Voltage Supply Voltage Supply Voltage
2 GHz Limiting Amplifier
Dia Pad Assignments
F0321818B
No. (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) * * * *
Symbol VDD2 VOUT+ VDD2 VOUTVDD2 VSS2 VDD2 VDD1 VSS1 LPF-
Center Coordinates(m) (160,80) (390,80) (540,80) (690,80) (920,80) (1000,320) (1000,550) (1000,780) (1000,1090) (920,1330)
No. (11) (12) (13) (14) (15) (16) (17) (18) O A
Symbol VINVDD1 VIN+ LPF+ VSS1 VDD1 VDD2 VSS2
Center Coordinates(m) (690,1330) (540,1330) (390,1330) (160,1330) (80,1090) (80,780) (80,470) (80,240) (0,0) (1080,1410)
*
VDD1 is not connected to VDD2 in the bare chip IC. VSS1 is not connected to VSS2 in the bare chip IC. For +5 V users, we recommended the Pads of No.16,17 are connected to power supply pads (+5 V) and the pads of No. 6, 9,15,18 are connected to GND pads. We recommend that unused input pin should be terminated to GND via coupling capacitor and 50 ohm load. Example : (unused input pin) (coupling capacitor) (50 ohm load) (GND) On the back of the bare die, we mount it on GND but no problem for mounted on VSS.
2 GHz Limiting Amplifier
Test Circuits
F0321818B
1) AC Characteristics
0.1F 50 LPFVINVIN+ LPF+ 0.1F VSS VOUTVOUT+ VDD 0.1 F VDD Pin =-40dBm 50 Vector Network Analyzer 50 2200 pF 50
*
F0321818B
*
2) Limiting Characteristics
0.1F 50 LPFVINVIN+ LPF+ 0.1F VDD Pulse Pattern Generator Sampling CLOCK Oscilloscope 50 VSS VOUTVOUT+ VDD 0.1 F 2200 pF 50
* *
F0321818B
* *
Attenuator
DATA
* DC BLOCK (PICOSECIND PULSE LABS, MODEL 5501)
2 GHz Limiting Amplifier
Typical AC Characteristics (1) Gain
F0321818B
Ta =25 C, VDD =+5 V, VSS =GND, Pin =-40 dBm, RL =50 , 300 kHz-3 GHz
(dB) 27
18
9
0 1M 10M 100M Frequency (Hz) 1G
(2) Dependence of Gain and High Frequency Cutoff on Power Supply Variations Ta =25 C, VDD =-5 V, VSS =GND, Pin =-40 dBm, RL =50 , 300 kHz-3 GHz
Gain (dB)
23 2.20 2.18 2.16 21 2.14 20 2.12 2.10 4.5
High Frequency Cut-off (GHz)
22
19 4.5
5.0 VDD(V)
5.5
5.0 VDD(V)
5.5
2 GHz Limiting Amplifier
Typical AC Characteristics (3) VSWR's
F0321818B
Ta =25 C, VDD =+5 V, VSS =GND, Pin =-40 dBm, RL =50 , 300 kHz - 3 GHz
6 5 4 3 2 1
[at VIN+]
6 5 4 3 2 1
[at VOUT+]
1M
10M
100M
1G
1M
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
*Almost same characteristics is exhibited at VIN-
*Almost same characteristics is exhibited at VOUT-
(4) S parameters on Smith Chart Ta =25 C, VDD =+5 V, VSS =GND, Pin =-40 dBm, RL =50 S11 at VIN+ S22 at VOUT+
START 100 MHz
STOP 3 GHz
START 100 MHz
STOP 3 GHz
2 GHz Limiting Amplifier
Typical Limiting Characteristics
F0321818B
(1) Eye diagrams for 2.5 Gb/s NRZ Pseudo-random Data Response 223-1, Ta = 25 C, VDD =5 V, VSS =GND, RL =50 (a) VIN+ = 5 mVp-p
10 mV/div
100 psec/div (b) VIN+ = 50 mVp-p
100 mV/div
100 psec/div (c) VIN+ = 500 mVp-p
100 mV/div
100 psec/div
2 GHz Limiting Amplifier
General Description
F0321818B
A post-amplifier is positioned between a preamplifier (an amplifier for a faint photocurrent from PIN photo diode) and a decision circuit (a circuit to discriminate the logic level of the received signal), enlarging the output signal from the preamplifier to a higher level to discriminate the logic level. The input signal amplitude of the post-amplifier, meaning the output signal of the preamplifier, varies widely, because the optical signal power received by the PIN photo diode depends on the length of the transmission line. Therefore, the post-amplifier should function to output an almost constant signal level under widely varying input voltage. This is called a limiting function, and the F0321818B provides excellent limiting characteristics. As shown in the data sheet, the increase of only 200 mV (400 mV600 mV) in the output voltage can be observed even if the 2.5 Gps input signal varies widely from 50 mV to 500 mV Wide use analog IC's having satisfactory limiting functions as described above can not be found except for the F0321818B. Customized IC's for each application or a circuit designed by discrete transistors are believed to have been developed.
Post Matching Input/output VSWR's of the F0321818B are well-designed for 50 , typically showing excellent VSWR's of 1.1:1. Therefore, the F0321818B can be applied for 50 systems with no external parts. Furthermore, the fine VSWR characteristics provide stable operation even for cascade connections of two IC's for a higher gain. The excellent VSWR characteristics of the F0321818B gives full play in a clock recovery system using SAW filters, because the impedance mismatch has a significant effect on the quality of the recovered clock signal.
Gain Consideration The F0321818B has a small signal gain of 20 dB. A too high gain can be harmful because of parasitic oscillation. If a slightly higher gain is needed, a 6 dB higher gain of 26 dB can be obtained by a high impedance termination instead of a 50 load. A double gain can be achieved by simple cascade connection if a still higher gain is required.
2 GHz Limiting Amplifier
Noise Performance
F0321818B
The F0321818B based on the GaAs FET fabrication process intrinsically has more excellent low-noise characteristics compared with IC's based on the silicon bipolar process. Many transmission systems often demand superior signal-to-noise ratio; the F0321818B is the best choice for such applications. The differential circuit configuration in the input and output enable a complete differential operation to reduce common mode noise: simple single ended input and output operation is also available.
LPF+ & LPFThe F0321818B has two terminals, LPF+ and LPF-, for AC ground. These terminals are connected to ground by a capacitor. The time constant of the feedback loop in the F0321818B depends on the capacitor, giving the lower frequency cutoff of the circuit by the large capacitor. A 0.1 micro farad is employed for conventional applications.
Die-Chip Description The F0321818B is shipped like the die-chip described above. The die thickness is typically 450 m 20 m with the available pad size uncovered by a passivation film of 95 m square. The material of the pads is TiW/Pt/Au and the backside is metalized by Ti/Au.
Assembling Condition SEI recommends the assembling process as shown below and affirms sufficient wirepull and die-shear strength. The heating time of one minutes at the temperature of 310 C gave satisfactory results for die-bonding with AuSn performs. The heating and ultrasonic wire-bonding at the temperature of 150 C by a ball-bonding machine is effective.
2 GHz Limiting Amplifier
Quality Assurance
F0321818B
For the Die-chip products, there is only one technically inevitable drawback in terms of quality assurance which is to be impossible of the burn-in test for screening owing to dieshipment. SEI will not ship them if customers do not agree on this point. On the other hand, the lot assurance test is performed completely without any problems according to SEI's authorized rules. A microscope inspection is conducted in conformance with the MIL-STD883C Method 2010.7.
Precautions Owing to their small dimensions, the GaAs FET's from which the F0321818B is designed are easily damaged or destroyed if subjected to large transient voltages. Such transients can be generated by power supplies when switched on if not properly decoupled. It is also possible to induce spikes from static-electricity-charged operations or ungrounded equipment.
Electron Device Department

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